As part of semiconductor device processing, a number of discrete devices and integrated circuits (“IC” or “ICs”) are formed on a wafer, or substrate, made from a semiconductive material, such as silicon. Generally, discrete devices and ICs are formed with layers of materials that have semiconductive, conductive, and/or insulative properties. These materials are deposited, doped, etched, or otherwise used to form ICs in individual regions on the wafer that are called die or dies. The dies are then diced (separated from each other) and packaged.
Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are one type of semiconductor device. Often, power MOSFETs are used as electrical switches and, when turned on, require the amount on-resistance (RDSon) to be minimized for optimum performance. But as the performance requirements for power MOSFETS increase, so does the need to minimize the RDSon.
RDSon depends, in part, on the resistance of the semiconductor substrate (typically a silicon wafer) containing the structure of the MOSFET. Some attempts have been made to reduce the substrate resistance by grinding the wafer to reduce its thickness as much as possible. While reducing the thickness reduces the substrate resistance, the minimum thickness that can be obtained by the grinding process is limited by the breakage of the wafer and other manufacturing problems.
Other attempts to reduce the substrate resistance have used localized wafer thinning, typically by forming enclosed holes 5 (as shown in FIG. 1a) or channels 10 (as shown in FIG. 1b) in local areas of the backside 15 of the wafer 20. But the enclosed hole design of FIG. 1a can require additional processing to avoid the air traps that can be formed when refilling the holes with a desired material. As well, the enclosed hole design can require front-back alignment for conventional saw process used in dicing because the conductive material in the holes can hinder the sawing action.
The channel design of FIG. 1b also has some drawbacks that limit its adoption. With this design, the wafer strength is significantly lower because of long cleavage line that runs across wafer or die, making the wafer or die prone to cleavage or breakage. As well, with this design, the wafer can warp along the channel direction. And higher magnitude and non-uniformity in the wafer warp is often expected with this design.